Often, it is necessary to operate a phase-locked loop with a relatively low loop-gain. A typical situation may be, for example, to maintain loop stability in the presence of multi-pole loop filters. When loop-gain is low, it is possible for the phase difference between a reference signal and an input signal to exceed the maximum phase difference allowed for the linear operation of a phase detector. Since the phase difference that may appear at a phase detector is inversely proportional to the loop-gain, the probability that, as the loop-gain is lowered, the phase difference between the reference signal and the input signal will exceed the maximum phase difference permitted by the phase detector is quite high.
One solution may be to use charge-pump type phase detectors in all situations where low loop-gain is required. However, charge-pump type phase detectors are often less desirable than sample-and-hold type phase detectors because charge-pump type phase detectors may exhibit undesirable responses in certain implementations due to an extra integrator inherent in the loop. Additionally, sample-and-hold type phase detectors offer a wider operational bandwidth since charge-pump type phase detectors exhibit increased reference frequency spurs. Accordingly, a need exists in the art for a sample-and-hold type phase detector having a wide phase range to facilitate linear operation of low loop-gain phase-locked loops.